(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method that allows creating layers of interconnect metal containing copper without the use of a conventional barrier layer.
(2) Description of the Prior Art
Semiconductor device performance improvements are typically achieved by device miniaturization and by increasing the packaging density of created semiconductor packages. With the continued decrease in device dimensions, device interconnect methods and materials are becoming an increasingly more importance part of creating packaged semiconductor devices.
The selection of insulation materials and the selection of the materials that are used for the creation of interconnect metal continue to be explored as part of a continuing effort to improve device performance. In this respect for instance methods and materials are explored that allow for the creation of low-k dielectric interfaces between adjacent layers of interconnect metal. In addition, the materials that are used for the creation of the interconnect metal, such as interconnect vias and interconnect traces, continues to present a challenge.
For the use as an interconnect medium, copper has increasingly gained acceptance and is increasingly used for this purpose. Copper is known to have a relatively low cost and a low resistivity, copper however has a relatively large diffusion coefficient into silicon dioxide and silicon. Copper from an interconnect may diffuse into a surrounding silicon dioxide layer, causing the dielectric to become conductive and decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore conventionally encapsulated by at least one layer of diffusion barrier material that prevents diffusion of the copper into the surrounding dielectric such as a layer of silicon dioxide. Silicon nitride is frequently used as a diffusion barrier layer for copper, the disadvantage of this approach is that metal interconnects preferably should not lie over a silicon nitride layer since the silicon nitride layer has a relatively high dielectric constant when compared with silicon dioxide, causing an undesirable increase in the capacitance between the interconnect metal and the underlying substrate. Copper is also known to have low adhesive strength to various insulating layers and is difficult to pattern by masking and etching a blanket layer of copper in order to create intricate structural circuit elements.
To create conductive interconnect lines and vias, the damascene or dual damascene process is frequently used. For the creation of Very and Ultra Large Scale Integrated devices using the dual damascene process, a layer of insulating or dielectric material is patterned and developed, creating several thousand openings there-through for conductive interconnect traces and vias. These openings are simultaneously filled with a metal, conventionally aluminum with more recently developments using copper, the in this manner created metal interconnects serve to interconnect active and/or passive elements of the integrated circuit.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed.
The invention concentrates on using copper as a metal interconnect medium, whereby the cost incurred by using copper can be reduced by eliminating the need for a conventional barrier layer. In addition, smooth sidewalls of the deposited copper can be obtained, reducing contact resistance. Porous sidewalls between the created copper layer and surrounding low-k dielectric are sealed, bonding between the created copper metal and the underlying interface is improved.
U.S. Pat. No. 6,110,817 (Tsai et al.) shows a carbon doped, copper containing interconnect.
U.S. Pat. No. 6,022,808 (Nogami et al.) shows a copper interconnect with doped copper for reduced electromigration.
U.S. Pat. No. 6,303,486 B1 (Park) reveals a copper interconnect process.
U.S. Pat. No. 6,346,479 B1 (Woo et al.) discloses a copper interconnect with doped copper.
A principle objective of the invention is to remove the need for a barrier layer that conventionally surrounds a deposited layer of copper.
Another objective of the invention is to smooth the sidewalls of a created layer of copper interconnect metal.
Yet another objective of the invention is to seal-off a porous interface between a deposited layer of copper and an underlying layer of semiconductor material.
A still further objective of the invention is to provide a method of creating copper interconnects such that yield and reliability performance are improved over conventional methods of creating copper interconnects.
In accordance with the objectives of the invention a new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.